Conditionally extract last element to vector register
From the second source vector register extract the last active element, and then replicate that element to destructively fill the destination and first source vector.
If there are no active elements then leave the destination and source vector unmodified.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | Pg | Zm | Zdn | |||||||||||
| B | |||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Zdn); integer m = UInt(Zm); boolean isBefore = TRUE;
| <Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = Z[dn]; bits(VL) operand2 = Z[m]; bits(VL) result; integer last = LastActiveElement(mask, esize); if last < 0 then result = operand1; else if !isBefore then last = last + 1; if last >= elements then last = 0; for e = 0 to elements-1 Elem[result, e, esize] = Elem[operand2, last, esize]; Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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