Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | op | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if size != '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | op | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '110' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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