Compare signed less than or equal to vector, setting the condition flags
Compare active signed integer elements in the first source vector being less than or equal to corresponding signed elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
This is a pseudo-instruction of CMP<cc> (vectors). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | size | 0 | Zm | 1 | 0 | 0 | Pg | Zn | 0 | Pd | ||||||||||||||
| ne | |||||||||||||||||||||||||||||||
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
The description of CMP<cc> (vectors) gives the operational pseudocode for this instruction.
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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