CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

In Armv8-A, this is an optional instruction, and in Armv8.1 it is mandatory for all implementations to implement it.

ID_AA64ISAR0_EL1.CRC32 indicates whether this instruction is supported.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |

sf | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | 1 | 0 | 1 | sz | Rn | Rd | |||||||||||||

C |

if !HaveCRCExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sf == '1' && sz != '11' then UNDEFINED; if sf == '0' && sz == '11' then UNDEFINED; integer size = 8 << UInt(sz); // 2-bit size field -> 8, 16, 32, 64 boolean crc32c = (C == '1');

<Wd> |
Is the 32-bit name of the general-purpose accumulator output register, encoded in the "Rd" field. |

<Wn> |
Is the 32-bit name of the general-purpose accumulator input register, encoded in the "Rn" field. |

<Xm> |
Is the 64-bit name of the general-purpose data source register, encoded in the "Rm" field. |

<Wm> |
Is the 32-bit name of the general-purpose data source register, encoded in the "Rm" field. |

bits(32) acc = X[n]; // accumulator bits(size) val = X[m]; // input value bits(32) poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>; bits(32+size) tempacc = BitReverse(acc) : Zeros(size); bits(size+32) tempval = BitReverse(val) : Zeros(32); // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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