Conditional Set Mask sets all bits of the destination register to 1 if the condition is TRUE, and otherwise sets all bits to 0.
This is an alias of CSINV. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | != 111x | 0 | 0 | 1 | 1 | 1 | 1 | 1 | Rd | |||||||
| op | Rm | cond | o2 | Rn | |||||||||||||||||||||||||||
is equivalent to
CSINV <Wd>, WZR, WZR, invert(<cond>)
and is always the preferred disassembly.
is equivalent to
CSINV <Xd>, XZR, XZR, invert(<cond>)
and is always the preferred disassembly.
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <cond> |
Is one of the standard conditions, excluding AL and NV, encoded in the "cond" field with its least significant bit inverted. |
The description of CSINV gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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