Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = esize; integer elements = 1; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UNDEFINED;
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | sz | 1 | Rm | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UNDEFINED;
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0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UNDEFINED;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | sz | 1 | Rm | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sz:Q == '10' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UNDEFINED;
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Hm> |
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
<V> |
Is a width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<m> |
Is the number of the second SIMD&FP source register, encoded in the "Rm" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(esize) element1; bits(esize) element2; boolean test_passed; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[m] else Zeros(); for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, fpcr); when CompareOp_GE test_passed = FPCompareGE(element1, element2, fpcr); when CompareOp_GT test_passed = FPCompareGT(element1, element2, fpcr); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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