Floating-point compare vector with zero
Compare active floating-point elements in the source vector with zero, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
The <cc> symbol specifies one of the standard ARM condition codes: EQ, GE, GT, LE, LT, or NE.
It has encodings from 6 classes: Equal , Greater than , Greater than or equal , Less than , Less than or equal and Not equal
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Pg | Zn | 0 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_EQ;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | Zn | 1 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_GT;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | Zn | 0 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_GE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Pg | Zn | 0 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_LT;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Pg | Zn | 1 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_LE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | Pg | Zn | 0 | Pd | ||||||||||
| eq | lt | ne | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Pd); SVECmp op = Cmp_NE;
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n] else Zeros(); bits(PL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(esize) element = Elem[operand, e, esize]; boolean res; case op of when Cmp_EQ res = FPCompareEQ(element, 0<esize-1:0>, FPCR[]); when Cmp_GE res = FPCompareGE(element, 0<esize-1:0>, FPCR[]); when Cmp_GT res = FPCompareGT(element, 0<esize-1:0>, FPCR[]); when Cmp_NE res = FPCompareNE(element, 0<esize-1:0>, FPCR[]); when Cmp_LT res = FPCompareGT(0<esize-1:0>, element, FPCR[]); when Cmp_LE res = FPCompareGE(0<esize-1:0>, element, FPCR[]); ElemP[result, e, esize] = if res then '1' else '0'; else ElemP[result, e, esize] = '0'; P[d] = result;
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register written by this instruction might be significantly delayed.
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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