Floating-point Convert precision (scalar). This instruction converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 0 | 0 | 1 | opc | 1 | 0 | 0 | 0 | 0 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); integer srcsize; integer dstsize; if ftype == opc then UNDEFINED; case ftype of when '00' srcsize = 32; when '01' srcsize = 64; when '10' UNDEFINED; when '11' srcsize = 16; case opc of when '00' dstsize = 32; when '01' dstsize = 64; when '10' UNDEFINED; when '11' dstsize = 16;
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Dn> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPEnabled64(); bits(srcsize) operand = V[n]; FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); Elem[result, 0, dstsize] = FPConvert(operand, fpcr); V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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