FCVTNS (vector)

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision

Scalar half precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0101111001111001101010RnRd
Uo2o1

FCVTNS <Hd>, <Hn>

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Scalar single-precision and double-precision

313029282726252423222120191817161514131211109876543210
010111100sz100001101010RnRd
Uo2o1

FCVTNS <V><d>, <V><n>

integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector half precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0Q00111001111001101010RnRd
Uo2o1

FCVTNS <Vd>.<T>, <Vn>.<T>

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector single-precision and double-precision

313029282726252423222120191817161514131211109876543210
0Q0011100sz100001101010RnRd
Uo2o1

FCVTNS <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is a width specifier, encoded in sz:

sz <V>
0 S
1 D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

For the half-precision variant: is an arrangement specifier, encoded in Q:

Q <T>
0 4H
1 8H

For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:

sz Q <T>
0 0 2S
0 1 4S
1 0 RESERVED
1 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(esize) element; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPToFixed(element, 0, unsigned, fpcr, rounding); V[d] = result;


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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