Floating-point down convert, rounding to odd (predicated)
Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the even-numbered 32-bit elements of the destination vector, while setting the odd-numbered elements to zero. Inactive elements in the destination vector register remain unmodified.
Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 32;
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n] else Zeros(); bits(VL) result = Z[d]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(esize) element = Elem[operand, e, esize]; bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR[], FPRounding_ODD); Elem[result, e, esize] = ZeroExtend(res); Z[d] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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