FCVTZU (vector, integer) -- A64

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Scalar half precision
(FEAT_FP16)

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Scalar single-precision and double-precision

integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector half precision
(FEAT_FP16)

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector single-precision and double-precision

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Assembler Symbols

<Hd>	Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>	Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is a width specifier, encoded in sz:

sz	<V>
0	S
1	D

<d>	Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>	Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

For the half-precision variant: is an arrangement specifier, encoded in Q:

Q	<T>
0	4H
1	8H

For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:

sz	Q	<T>
0	0	2S
0	1	4S
1	0	RESERVED
1	1	2D

<Vn>	Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(esize) element; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPToFixed(element, 0, unsigned, fpcr, rounding); V[d] = result;

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	1	1	1	1	0	1	1	1	1	1	0	0	1	1	0	1	1	1	0	Rn					Rd
		U						o2											o1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	1	1	1	1	0	1	sz	1	0	0	0	0	1	1	0	1	1	1	0	Rn					Rd
		U						o2											o1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	1	0	1	1	1	0	1	1	1	1	1	0	0	1	1	0	1	1	1	0	Rn					Rd
		U						o2											o1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	1	0	1	1	1	0	1	sz	1	0	0	0	0	1	1	0	1	1	1	0	Rn					Rd
		U						o2											o1