FMINV

Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

Half-precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0Q00111010110000111110RnRd
o1

FMINV <V><d>, <Vn>.<T>

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; ReduceOp op = if o1 == '1' then ReduceOp_FMIN else ReduceOp_FMAX;

Single-precision and double-precision

313029282726252423222120191817161514131211109876543210
0Q1011101sz110000111110RnRd
o1

FMINV <V><d>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q != '01' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; ReduceOp op = if o1 == '1' then ReduceOp_FMIN else ReduceOp_FMAX;

Assembler Symbols

<V>

For the half-precision variant: is the destination width specifier, H.

For the single-precision and double-precision variant: is the destination width specifier, encoded in sz:

sz <V>
0 S
1 RESERVED
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T>

For the half-precision variant: is an arrangement specifier, encoded in Q:

Q <T>
0 4H
1 8H

For the single-precision and double-precision variant: is an arrangement specifier, encoded in Q:sz:

Q sz <T>
0 x RESERVED
1 0 4S
1 1 RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; V[d] = Reduce(op, operand, esize);


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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