Floating-point fused Multiply-Add to accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results in the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar, half-precision , Scalar, single-precision and double-precision , Vector, half-precision and Vector, single-precision and double-precision
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 0 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
o2 |
if !HaveFP16Ext() then UNDEFINED; integer idxdsize = if H == '1' then 128 else 64; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer index = UInt(H:L:M); integer esize = 16; integer datasize = esize; integer elements = 1; boolean sub_op = (o2 == '1');
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 0 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
o2 |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; boolean sub_op = (o2 == '1');
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0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 0 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
o2 |
if !HaveFP16Ext() then UNDEFINED; integer idxdsize = if H == '1' then 128 else 64; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer index = UInt(H:L:M); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean sub_op = (o2 == '1');
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0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 0 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
o2 |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); if sz:Q == '10' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean sub_op = (o2 == '1');
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<V> |
Is a width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
For the half-precision variant: is the name of the second SIMD&FP source register, in the range V0 to V15, encoded in the "Rm" field. |
For the single-precision and double-precision variant: is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields. |
<Ts> |
Is an element size specifier,
encoded in
|
<index> |
For the half-precision variant: is the element index, in the range 0 to 7, encoded in the "H:L:M" fields. | ||||||||||||
For the single-precision and double-precision variant: is the element index,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if sub_op then element1 = FPNeg(element1); Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, fpcr); V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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