Floating-point outer product and accumulate
The single-precision variant works with a 32-bit element ZA tile.
The double-precision variant works with a 64-bit element ZA tile.
These instructions generate an outer product of the first source vector and the second source vector. In case of the single-precision variant, the first source is SVLS×1 vector and the second source is 1×SVLS vector. In case of the double-precision variant, the first source is SVLD×1 vector and the second source is 1×SVLD vector.
Each source vector is independently predicated by a corresponding predicate register. When either source vector element is Inactive the corresponding destination tile element remains unmodified.
The resulting outer product, SVLS×SVLS in case of single-precision variant or SVLD×SVLD in case of double-precision variant, is then destructively added to the destination tile. This is equivalent to performing a single multiply-accumulate to each of the destination tile elements.
This instruction follows SME floating-point numerical behaviors.
ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented.
It has encodings from 2 classes: Single-precision and Double-precision
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda | |||||||||||||
S |
if !HaveSME() then UNDEFINED; integer esize = 32; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(ZAda); boolean sub_op = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | ZAda | ||||||||||||||
S |
if !HaveSMEF64F64() then UNDEFINED; integer esize = 64; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(ZAda); boolean sub_op = FALSE;
<Pn> |
Is the name of the first source scalable predicate register P0-P7, encoded in the "Pn" field. |
<Pm> |
Is the name of the second source scalable predicate register P0-P7, encoded in the "Pm" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckStreamingSVEAndZAEnabled(); integer dim = VL DIV esize; bits(PL) mask1 = P[a]; bits(PL) mask2 = P[b]; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(dim*dim*esize) operand3 = ZAtile[da, esize]; bits(dim*dim*esize) result; for row = 0 to dim-1 for col = 0 to dim-1 bits(esize) element1 = Elem[operand1, row, esize]; bits(esize) element2 = Elem[operand2, col, esize]; bits(esize) element3 = Elem[operand3, row*dim+col, esize]; if ElemP[mask1, row, esize] == '1' && ElemP[mask2, col, esize] == '1' then if sub_op then element1 = FPNeg(element1); Elem[result, row*dim+col, esize] = FPMulAdd_ZA(element3, element1, element2, FPCR[]); else Elem[result, row*dim+col, esize] = element3; ZAtile[da, esize] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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