Floating-point Round to 64-bit Integer, using current rounding mode (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.
A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | x | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||
ftype | op |
if !HaveFrintExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize; case ftype of when '00' esize = 32; when '01' esize = 64; when '1x' UNDEFINED; integer intsize = if op<1> == '0' then 32 else 64; FPRounding rounding = if op<0> == '0' then FPRounding_ZERO else FPRoundingMode(FPCR[]);
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Dn> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPEnabled64(); FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); bits(esize) operand = V[n]; Elem[result, 0, esize] = FPRoundIntN(operand, fpcr, rounding, intsize); V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.