INSR (SIMD&FP scalar)

Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. This instruction is unpredicated.

if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer dn = UInt(Zdn); integer m = UInt(Vm);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<V>

Is a width specifier, encoded in size:

size	<V>
00	B
01	H
10	S
11	D

<m>	Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.

Operation

CheckSVEEnabled(); bits(VL) dest = Z[dn]; bits(esize) src = V[m]; Z[dn] = dest<VL-esize-1:0> : src;

Operational information

If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

The MOVPRFX instruction must be unpredicated.
The MOVPRFX instruction must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		1	1	0	1	0	0	0	0	1	1	1	0	Vm					Zdn