Contiguous load and replicate eight words (immediate index)
Load eight contiguous words to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address.
Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero.
The resulting 256-bit vector is then replicated to fill the destination vector. The instruction requires that the current vector length is at least 256 bits, and if the current vector length is not an integer multiple of 256 bits then the trailing bits in the destination vector are set to zero.
Only the first eight predicate elements are used and higher numbered predicate elements are ignored.
ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | imm4 | 0 | 0 | 1 | Pg | Rn | Zt | |||||||||||||
| msz<1> | msz<0> | ssz | |||||||||||||||||||||||||||||
if !HaveSVE() || !HaveSVEFP64MatMulExt() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 32; integer offset = SInt(imm4);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field. |
CheckNonStreamingSVEEnabled(); if VL < 256 then UNDEFINED; integer elements = 256 DIV esize; bits(64) base; bits(PL) mask = P[g]; // low bits only bits(256) result; constant integer mbytes = esize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(n != 31); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer eoff = (offset * elements) + e; bits(64) addr = base + eoff * mbytes; Elem[result, e, esize] = Mem[addr, mbytes, AccType_NORMAL]; else Elem[result, e, esize] = Zeros(); Z[t] = ZeroExtend(Replicate(result, VL DIV 256), VL);
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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