LD1SW (scalar plus vector)

Gather load signed words to vector (vector index)

Gather load of signed words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.

It has encodings from 4 classes: 32-bit unpacked scaled offset , 32-bit unpacked unscaled offset , 64-bit scaled offset and 64-bit unscaled offset

32-bit unpacked scaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 32; boolean unsigned = FALSE; boolean offs_unsigned = xs == '0'; integer scale = 2;

32-bit unpacked unscaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 32; boolean unsigned = FALSE; boolean offs_unsigned = xs == '0'; integer scale = 0;

64-bit scaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 64; boolean unsigned = FALSE; boolean offs_unsigned = TRUE; integer scale = 2;

64-bit unscaled offset

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 64; boolean unsigned = FALSE; boolean offs_unsigned = TRUE; integer scale = 0;