LDFF1B (scalar plus scalar)

Contiguous load first-fault unsigned bytes to vector (scalar index)

Contiguous load with first-faulting behavior of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

It has encodings from 4 classes: 8-bit element , 16-bit element , 32-bit element and 64-bit element

8-bit element

313029282726252423222120191817161514131211109876543210
10100100000Rm011PgRnZt
dtype<3:1>dtype<0>

LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 8; integer msize = 8; boolean unsigned = TRUE;

16-bit element

313029282726252423222120191817161514131211109876543210
10100100001Rm011PgRnZt
dtype<3:1>dtype<0>

LDFF1B { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 16; integer msize = 8; boolean unsigned = TRUE;

32-bit element

313029282726252423222120191817161514131211109876543210
10100100010Rm011PgRnZt
dtype<3:1>dtype<0>

LDFF1B { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 32; integer msize = 8; boolean unsigned = TRUE;

64-bit element

313029282726252423222120191817161514131211109876543210
10100100011Rm011PgRnZt
dtype<3:1>dtype<0>

LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 64; integer msize = 8; boolean unsigned = TRUE;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operation

CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; bits(VL) result; bits(VL) orig = Z[t]; bits(msize) data; bits(64) offset; constant integer mbytes = msize DIV 8; boolean first = TRUE; boolean fault = FALSE; boolean faulted = FALSE; boolean unknown = FALSE; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; offset = X[m]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(64) addr = base + (UInt(offset) + e) * mbytes; if first then // Mem[] will not return if a fault is detected for the first active element data = Mem[addr, mbytes, AccType_NORMAL]; first = FALSE; else // MemNF[] will return fault=TRUE if access is not performed for any reason (data, fault) = MemNF[addr, mbytes, AccType_CNOTFIRST]; else (data, fault) = (Zeros(msize), FALSE); // FFR elements set to FALSE following a supressed access/fault faulted = faulted || fault; if faulted then ElemFFR[e, esize] = '0'; // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE unknown = unknown || ElemFFR[e, esize] == '0'; if unknown then if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then Elem[result, e, esize] = Extend(data, esize, unsigned); elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then Elem[result, e, esize] = Zeros(); else // merge Elem[result, e, esize] = Elem[orig, e, esize]; else Elem[result, e, esize] = Extend(data, esize, unsigned); Z[t] = result;


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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