Load Tag Multiple reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.



LDGM <Xt>, [<Xn|SP>]

if !HaveMTE2Ext() then UNDEFINED; integer t = UInt(Xt); integer n = UInt(Xn);

Assembler Symbols


Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.


Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.


if PSTATE.EL == EL0 then UNDEFINED; bits(64) data = Zeros(64); bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; integer size = 4*(2^(UInt(GMID_EL1.BS))); address = Align(address,size); integer count = size >> LOG2_TAG_GRANULE; integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>); for i = 0 to count-1 bits(4) tag = AArch64.MemTag[address, AccType_NORMAL]; data<(index*4)+3:index*4> = tag; address = address + TAG_GRANULE; index = index + 1; X[t] = data;

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.