Load LOAcquire Register Halfword loads a halfword from memory, zero-extends it, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about memory accesses, see Load/Store addressing modes.

For this instruction, if the destination is WZR/XZR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.

No offset


LDLARH <Wt>, [<Xn|SP>{,#0}]

integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); // ignored by load/store single register integer s = UInt(Rs); // ignored by all loads and store-release AccType acctype = if o0 == '0' then AccType_LIMITEDORDERED else AccType_ORDERED; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize; boolean tag_checked = n != 31;

Assembler Symbols


Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.


Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.


bits(64) address; bits(datasize) data; constant integer dbytes = datasize DIV 8; if HaveMTE2Ext() then SetTagCheckedInstruction(tag_checked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; case memop of when MemOp_STORE data = X[t]; Mem[address, dbytes, acctype] = data; when MemOp_LOAD data = Mem[address, dbytes, acctype]; X[t] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.