Load vector register
Load a vector register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current vector register size in bytes. This instruction is unpredicated.
The load is performed as a stream of byte elements in ascending element order, without any endian conversion.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm9h | 0 | 1 | 0 | imm9l | Rn | Zt | |||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer imm = SInt(imm9h:imm9l);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. |
CheckSVEEnabled(); integer elements = VL DIV 8; bits(64) base; integer offset = imm * elements; bits(VL) result; if n == 31 then CheckSPAlignment(); if HaveMTEExt() then SetTagCheckedInstruction(FALSE); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; boolean aligned = AArch64.CheckAlignment(base + offset, 16, AccType_NORMAL, FALSE); for e = 0 to elements-1 Elem[result, e, 8] = AArch64.MemSingle[base + offset, 1, AccType_NORMAL, aligned]; offset = offset + 1; Z[t] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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