LDR

Load vector to ZA array

The ZA array vector is selected by the sum of the vector select register and an immediate, modulo the number of bytes in a Streaming SVE vector. The immediate is in the range 0 to 15. The memory address is generated by scalar base, plus the same optional immediate offset multiplied by the current vector length in bytes. This instruction is unpredicated.

The load is performed as a stream of byte elements in ascending element order, without any endian conversion.

This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.

SME
(FEAT_SME)

313029282726252423222120191817161514131211109876543210
11100001000000000Rv000Rn0imm4

LDR ZA[<Wv>, <imm>], [<Xn|SP>{, #<imm>, MUL VL}]

if !HaveSME() then UNDEFINED; integer n = UInt(Rn); integer v = UInt('011':Rv); integer imm = UInt(imm4);

Assembler Symbols

<Wv>

Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field.

<imm>

Is the vector select offset and optional memory offset, in the range 0 to 15, defaulting to 0, encoded in the "imm4" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

CheckSMEAndZAEnabled(); integer dim = SVL DIV 8; bits(64) base; integer offset = imm * dim; bits(SVL) result; bits(32) idx = X[v]; integer vec = (UInt(idx) + imm) MOD dim; if HaveTME() && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if n == 31 then if HaveMTEExt() then SetTagCheckedInstruction(FALSE); CheckSPAlignment(); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; boolean aligned = AArch64.CheckAlignment(base + offset, 16, AccType_NORMAL, FALSE); for e = 0 to dim-1 Elem[result, e, 8] = AArch64.MemSingle[base + offset, 1, AccType_NORMAL, aligned]; offset = offset + 1; ZAvector[vec] = result;


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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