LDRH (register)

Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
01111000011RmoptionS10RnRt
sizeopc

LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(size); if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then scale else 0;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm>

When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>

When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

<extend>

Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted. encoded in option:

option <extend>
010 UXTW
011 LSL
110 SXTW
111 SXTX
<amount>

Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S <amount>
0 #0
1 #1

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm); AccType acctype = AccType_NORMAL; MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = if size == '11' then 64 else 32; signed = FALSE; else if size == '11' then memop = MemOp_PREFETCH; if opc<0> == '1' then UNDEFINED; else // sign-extending load memop = MemOp_LOAD; if size == '10' && opc<0> == '1' then UNDEFINED; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; integer datasize = 8 << scale; boolean tag_checked = memop != MemOp_PREFETCH; boolean wb_unknown = FALSE; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if memop == MemOp_STORE && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

Operation

bits(64) offset = ExtendReg(m, extend_type, shift); bits(64) address; bits(datasize) data; if HaveMTE2Ext() then SetTagCheckedInstruction(tag_checked); if n == 31 then if memop != MemOp_PREFETCH then CheckSPAlignment(); address = SP[]; else address = X[n]; if ! postindex then address = address + offset; case memop of when MemOp_STORE if rt_unknown then data = bits(datasize) UNKNOWN; else data = X[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD data = Mem[address, datasize DIV 8, acctype]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCH Prefetch(address, t<4:0>); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = address + offset; if n == 31 then SP[] = address; else X[n] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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