LDRSH (immediate)

Load Register Signed Halfword (immediate) loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

Post-index

313029282726252423222120191817161514131211109876543210
011110001x0imm901RnRt
sizeopc

32-bit (opc == 11)

LDRSH <Wt>, [<Xn|SP>], #<simm>

64-bit (opc == 10)

LDRSH <Xt>, [<Xn|SP>], #<simm>

boolean wback = TRUE; boolean postindex = TRUE; integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Pre-index

313029282726252423222120191817161514131211109876543210
011110001x0imm911RnRt
sizeopc

32-bit (opc == 11)

LDRSH <Wt>, [<Xn|SP>, #<simm>]!

64-bit (opc == 10)

LDRSH <Xt>, [<Xn|SP>, #<simm>]!

boolean wback = TRUE; boolean postindex = FALSE; integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Unsigned offset

313029282726252423222120191817161514131211109876543210
011110011ximm12RnRt
sizeopc

32-bit (opc == 11)

LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]

64-bit (opc == 10)

LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(size); bits(64) offset = LSL(ZeroExtend(imm12, 64), scale);

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRSH (immediate).

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<pimm>

Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); AccType acctype = AccType_NORMAL; MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = if size == '11' then 64 else 32; signed = FALSE; else if size == '11' then UNDEFINED; else // sign-extending load memop = MemOp_LOAD; if size == '10' && opc<0> == '1' then UNDEFINED; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; integer datasize = 8 << scale; boolean tag_checked = memop != MemOp_PREFETCH && (wback || n != 31); boolean wb_unknown = FALSE; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if memop == MemOp_STORE && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

Operation

bits(64) address; bits(datasize) data; if HaveMTE2Ext() then SetTagCheckedInstruction(tag_checked); if n == 31 then if memop != MemOp_PREFETCH then CheckSPAlignment(); address = SP[]; else address = X[n]; if ! postindex then address = address + offset; case memop of when MemOp_STORE if rt_unknown then data = bits(datasize) UNKNOWN; else data = X[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD data = Mem[address, datasize DIV 8, acctype]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCH Prefetch(address, t<4:0>); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = address + offset; if n == 31 then SP[] = address; else X[n] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.