Move signed immediate to vector elements (unpredicated)
Unconditionally broadcast the signed integer immediate into each element of the destination vector. This instruction is unpredicated.
The immediate operand is a signed value in the range -128 to +127, and for element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512 (excluding 0).
The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<simm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".
This is an alias of DUP (immediate). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | sh | imm8 | Zd | ||||||||||||
MOV <Zd>.<T>, #<imm>{, <shift>}
is equivalent to
DUP <Zd>.<T>, #<imm>{, <shift>}
and is always the preferred disassembly.
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <imm> |
Is a signed immediate in the range -128 to 127, encoded in the "imm8" field. |
| <shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
|
The description of DUP (immediate) gives the operational pseudocode for this instruction.
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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