Move general-purpose register to a vector element. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.
This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This is an alias of INS (general). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
MOV <Vd>.<Ts>[<index>], <R><n>
is equivalent to
INS <Vd>.<Ts>[<index>], <R><n>
and is always the preferred disassembly.
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Ts> |
Is an element size specifier,
encoded in
|
| <index> |
Is the element index
encoded in
|
| <R> |
Is the width specifier for the general-purpose source register,
encoded in
|
| <n> |
Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field. |
The description of INS (general) gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.