Move predicate (unpredicated), setting the condition flags
Read all elements from the source predicate and place in the destination predicate. This instruction is unpredicated. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
This is an alias of ORRS. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | Pm | 0 | 1 | Pg | 0 | Pn | 0 | Pd | ||||||||||||
| S | |||||||||||||||||||||||||||||||
is equivalent to
ORRS <Pd>.B, <Pn>/Z, <Pn>.B, <Pn>.B
and is the preferred disassembly when S == '1' && Pn == Pm && Pm == Pg.
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
The description of ORRS gives the operational pseudocode for this instruction.
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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