Polynomial multiply long (top)
Polynomial multiply over [0, 1] the corresponding odd-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.
ID_AA64ZFR0_EL1.AES indicates whether the instruction variant with 64-bit source and 128-bit destination elements is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | size | 0 | Zm | 0 | 1 | 1 | 0 | 1 | 1 | Zn | Zd | |||||||||||||
| U | T | ||||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; if size == '00' && !HaveSVE2PMULL128() then UNDEFINED; case size of when '00' esize = 128; when '01' esize = 16; when '10' UNDEFINED; when '11' esize = 64; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(esize DIV 2) element1 = Elem[operand1, 2*e + 1, esize DIV 2]; bits(esize DIV 2) element2 = Elem[operand2, 2*e + 1, esize DIV 2]; Elem[result, e, esize] = PolynomialMult(element1, element2); Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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