Gather prefetch bytes (vector plus immediate)
Gather prefetch of bytes from the active memory addresses generated by a vector base plus immediate index. The index is in the range 0 to 31. Inactive addresses are not prefetched from memory.
The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).
It has encodings from 2 classes: 32-bit element and 64-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop | |||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSVE() then UNDEFINED; integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 0; integer offset = UInt(imm5);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop | |||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !HaveSVE() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 0; integer offset = UInt(imm5);
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field. |
CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) base; if AnyActiveElement(mask, esize) then base = Z[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(64) addr = ZeroExtend(Elem[base, e, esize], 64) + (offset << scale); Hint_Prefetch(addr, pref_hint, level, stream);
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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