Gather prefetch words (scalar plus vector)
Gather prefetch of words from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then multiplied by 4. Inactive addresses are not prefetched from memory.
The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).
It has encodings from 3 classes: 32-bit scaled offset , 32-bit unpacked scaled offset and 64-bit scaled offset
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | xs | 1 | Zm | 0 | 1 | 0 | Pg | Rn | 0 | prfop | |||||||||||||
msz<1> | msz<0> |
if !HaveSVE() then UNDEFINED; integer esize = 32; integer g = UInt(Pg); integer n = UInt(Rn); integer m = UInt(Zm); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer offs_size = 32; boolean offs_unsigned = (xs == '0'); integer scale = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | xs | 1 | Zm | 0 | 1 | 0 | Pg | Rn | 0 | prfop | |||||||||||||
msz<1> | msz<0> |
if !HaveSVE() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Rn); integer m = UInt(Zm); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer offs_size = 32; boolean offs_unsigned = (xs == '0'); integer scale = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 1 | 1 | 0 | Pg | Rn | 0 | prfop | |||||||||||||
msz<1> | msz<0> |
if !HaveSVE() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Rn); integer m = UInt(Zm); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer offs_size = 64; boolean offs_unsigned = TRUE; integer scale = 2;
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
<mod> |
Is the index extend and shift specifier,
encoded in
|
CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(64) base; bits(VL) offset; if AnyActiveElement(mask, esize) then base = if n == 31 then SP[] else X[n]; offset = Z[m]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned); bits(64) addr = base + (off << scale); Hint_Prefetch(addr, pref_hint, level, stream);
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.