PSEL

Predicate select between predicate register or all-false

If the indexed element of the second source predicate is true, place the contents of the first source predicate register into the destination predicate register, otherwise set the destination predicate to all-false. The indexed element is determined by the sum of a general-purpose index register and an immediate, modulo the number of elements. Does not set the condition flags.

SVE2
(FEAT_SME)

313029282726252423222120191817161514131211109876543210
00100101i1tszh1tszlRv01Pn0Pm0Pd
S

PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]

if !HaveSME() then UNDEFINED; bits(5) imm5 = i1:tszh:tszl; integer esize; case tszh:tszl of when '0000' UNDEFINED; when '1000' esize = 64; imm = UInt(imm5<4>); when 'x100' esize = 32; imm = UInt(imm5<4:3>); when 'xx10' esize = 16; imm = UInt(imm5<4:2>); when 'xxx1' esize = 8; imm = UInt(imm5<4:1>); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer v = UInt('011':Rv);

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

<T>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <T>
0 000 RESERVED
x xx1 B
x x10 H
x 100 S
1 000 D
<Wv>

Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field.

<imm>

Is the element index, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl".

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) operand1 = P[n]; bits(PL) operand2 = P[m]; bits(32) idx = X[v]; integer element = (UInt(idx) + imm) MOD elements; bits(PL) result; if ElemP[operand2, element, esize] == '1' then result = operand1; else result = Zeros(); P[d] = result;

Operational information

If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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