PSSBB
Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address.
The semantics of the Physical Speculative Store Bypass Barrier are:
- When a load to a location appears in program order after the PSSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:
- The store is to the same location as the load.
- The store appears in program order before the PSSBB.
- When a load to a location appears in program order before the PSSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:
- The store is to the same location as the load.
- The store appears in program order after the PSSBB.
This is an alias of
DSB.
This means:
-
The encodings in this description are named to match the encodings of
DSB.
-
The description of
DSB
gives the operational pseudocode for this instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| | | | | CRm | | opc | |
PSSBB
is equivalent to
DSB #4
and is always the preferred disassembly.
Operation
The description of
DSB
gives the operational pseudocode for this instruction.
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d
; Build timestamp: 2021-10-06T11:41
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