REV64

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001110size100000000010RnRd
Uo0

REV64 <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); // size=esize: B(0), H(1), S(1), D(S) integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; // op=REVx: 64(0), 32(1), 16(2) bits(2) op = o0:U; // => op+size: // 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X // 32+B = 1, 32+H = 2, 32+S = X, 32+D = X // 16+B = 2, 16+H = X, 16+S = X, 16+D = X // 8+B = X, 8+H = X, 8+S = X, 8+D = X // => 3-(op+size) (index bits in group) // 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X // 32+B = 2, 32+H = 1, 32+S = X, 32+D = X // 16+B = 1, 16+H = X, 16+S = X, 16+D = X // 8+B = X, 8+H = X, 8+S = X, 8+D = X // index bits within group: 1, 2, 3 if UInt(op)+UInt(size) >= 3 then UNDEFINED; integer container_size; case op of when '10' container_size = 16; when '01' container_size = 32; when '00' container_size = 64; integer containers = datasize DIV container_size; integer elements_per_container = container_size DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in size:Q:

size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element = 0; integer rev_element; for c = 0 to containers-1 rev_element = element + elements_per_container - 1; for e = 0 to elements_per_container-1 Elem[result, rev_element, esize] = Elem[operand, element, esize]; element = element + 1; rev_element = rev_element - 1; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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