RMIF

Performs a rotation right of a value held in a general purpose register by an immediate value, and then inserts a selection of the bottom four bits of the result of the rotation into the PSTATE flags, under the control of a second immediate mask.

Integer
(FEAT_FlagM)

313029282726252423222120191817161514131211109876543210
10111010000imm600001Rn0mask
sf

RMIF <Xn>, #<shift>, #<mask>

if !HaveFlagManipulateExt() || sf != '1' then UNDEFINED; integer lsb = UInt(imm6); integer n = UInt(Rn);

Assembler Symbols

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<shift>

Is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,

<mask>

Is the flag bit mask, an immediate in the range 0 to 15, which selects the bits that are inserted into the NZCV condition flags, encoded in the "mask" field.

Operation

bits(4) tmp; bits(64) tmpreg = X[n]; tmp = (tmpreg:tmpreg)<lsb+3:lsb>; if mask<3> == '1' then PSTATE.N = tmp<3>; if mask<2> == '1' then PSTATE.Z = tmp<2>; if mask<1> == '1' then PSTATE.C = tmp<1>; if mask<0> == '1' then PSTATE.V = tmp<0>;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.