Signed add long (top)
Add the corresponding odd-numbered signed elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | size | 0 | Zm | 0 | 0 | 0 | 0 | 0 | 1 | Zn | Zd | |||||||||||||
| S | U | T | |||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer sel1 = 1; integer sel2 = 1; boolean unsigned = FALSE;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, 2*e + sel1, esize DIV 2], unsigned); integer element2 = Int(Elem[operand2, 2*e + sel2, esize DIV 2], unsigned); integer res = element1 + element2; Elem[result, e, esize] = res<esize-1:0>; Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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