Signed fixed-point Convert to Floating-point (scalar). This instruction converts the signed value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 0 | 0 | 0 | 0 | 1 | 0 | scale | Rn | Rd | ||||||||||||||
rmode | opcode |
integer d = UInt(Rd); integer n = UInt(Rn); integer intsize = if sf == '1' then 64 else 32; integer fltsize; FPConvOp op; FPRounding rounding; boolean unsigned; case ftype of when '00' fltsize = 32; when '01' fltsize = 64; when '10' UNDEFINED; when '11' if HaveFP16Ext() then fltsize = 16; else UNDEFINED; if sf == '0' && scale<5> == '0' then UNDEFINED; integer fracbits = 64 - UInt(scale); case opcode<2:1>:rmode of when '00 11' // FCVTZ rounding = FPRounding_ZERO; unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_FtoI; when '01 00' // [US]CVTF rounding = FPRoundingMode(FPCR[]); unsigned = (opcode<0> == '1'); op = FPConvOp_CVT_ItoF; otherwise UNDEFINED;
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
CheckFPEnabled64(); FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); integer fsize = if op == FPConvOp_CVT_ItoF && merge then 128 else fltsize; bits(fsize) fltval; bits(intsize) intval; case op of when FPConvOp_CVT_FtoI fltval = V[n]; intval = FPToFixed(fltval, fracbits, unsigned, fpcr, rounding); X[d] = intval; when FPConvOp_CVT_ItoF intval = X[n]; fltval = if merge then V[d] else Zeros(); Elem[fltval, 0, fltsize] = FixedToFP(intval, fracbits, unsigned, fpcr, rounding); V[d] = fltval;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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