Conditionally select elements from two vectors
Read active elements from the first source vector and inactive elements from the second source vector and place in the corresponding elements of the destination vector.
This instruction is used by the alias MOV (vector, predicated).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 1 | 1 | Pg | Zn | Zd | ||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
| Alias | Is preferred when |
|---|---|
| MOV (vector, predicated) | Zd == Zm |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n] else Zeros(); bits(VL) operand2 = if AnyActiveElement(NOT(mask), esize) then Z[m] else Zeros(); bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = Elem[operand1, e, esize]; else Elem[result, e, esize] = Elem[operand2, e, esize]; Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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