SETGPN, SETGMN, SETGEN -- A64

Memory Set with tag setting, non-temporal. These instructions perform a memory set using the value in the bottom byte of the source register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGPN, then SETGMN, and then SETGEN.

SETGPN performs some preconditioning of the arguments suitable for using the SETGMN instruction, and performs an implementation defined amount of the memory set. SETGMN performs an implementation defined amount of the memory set. SETGEN performs the last part of the memory set.

The inclusion of implementation defined amounts of memory set allows some optimization of the size that can be performed.

The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is implementation defined.

Integer
(FEAT_MOPS)

if !HaveFeatMOPS() then UNDEFINED; if !HaveMTEExt() then UNDEFINED; if sz != '00' then UNDEFINED; integer d = UInt(Rd); integer s = UInt(Rs); integer n = UInt(Rn); bits(2) options = op2<1:0>; MOPSStage stage; case op2<3:2> of when '00' stage = MOPSStage_Prologue; when '01' stage = MOPSStage_Main; when '10' stage = MOPSStage_Epilogue; otherwise UNDEFINED; if s == n || s == d || n == d then UNDEFINED; if d == 31 || n == 31 then UNDEFINED;

Assembler Symbols

<Xd>	For the epilogue and main variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
	For the prologue variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.

<Xn>	For the epilogue variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero at the end of the instruction, encoded in the "Rn" field.
	For the main variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
	For the prologue variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.

<Xs>	For the epilogue variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.
	For the main and prologue variant: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.

Operation

CheckMOPSEnabled(); bits(64) toaddress = X[d]; bits(64) setsize = X[n]; bits(8) data = X[s]; bits(64) stagesetsize; boolean is_setg = TRUE; integer B; if HaveMTE2Ext() then SetTagCheckedInstruction(FALSE); boolean supports_option_a = MemCpyOptionA(); acctype = MemSetAccessType(options); if stage == MOPSStage_Prologue then if setsize<63> == '1' then setsize = 0x7FFFFFFFFFFFFFF0<63:0>; if setsize != Zeros(64) && toaddress != Align(toaddress, TAG_GRANULE) then boolean iswrite = TRUE; boolean secondstage = FALSE; AArch64.Abort(toaddress, AlignmentFault(acctype, iswrite, secondstage)); if setsize != Align(setsize, TAG_GRANULE) then boolean iswrite = TRUE; boolean secondstage = FALSE; AArch64.Abort(toaddress, AlignmentFault(acctype, iswrite, secondstage)); if supports_option_a then PSTATE.C = '0'; toaddress = toaddress + setsize; setsize = Zeros(64) - setsize; else PSTATE.C = '1'; PSTATE.N = '0'; PSTATE.V = '0'; PSTATE.Z = '0'; stagesetsize = SETPreSizeChoice(toaddress, setsize, is_setg); assert stagesetsize<63> == setsize<63> || stagesetsize == Zeros(); assert stagesetsize<3:0> == '0000'; if SInt(setsize) > 0 then assert SInt(stagesetsize) <= SInt(setsize); else assert SInt(stagesetsize) >= SInt(setsize); else bits(64) postsize = SETPostSizeChoice(toaddress, setsize, is_setg); assert postsize<63> == setsize<63> || postsize == Zeros(); assert postsize<3:0> == '0000'; boolean zero_size_exceptions = MemSetZeroSizeCheck(); // Check if this version is consistent with the state of the call. if zero_size_exceptions || SInt(setsize) != 0 then if supports_option_a then if PSTATE.C == '1' then boolean wrong_option = TRUE; boolean from_epilogue = stage == MOPSStage_Epilogue; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); else if PSTATE.C == '0' then boolean wrong_option = TRUE; boolean from_epilogue = stage == MOPSStage_Epilogue; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); if stage == MOPSStage_Main then stagesetsize = setsize - postsize; if MemSetParametersIllformedM(toaddress, setsize, is_setg) then boolean wrong_option = FALSE; boolean from_epilogue = FALSE; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); else stagesetsize = postsize; if (setsize != postsize || MemSetParametersIllformedE(toaddress, setsize, is_setg)) then boolean wrong_option = FALSE; boolean from_epilogue = TRUE; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); if setsize != Zeros(64) && toaddress != Align(toaddress, TAG_GRANULE) then boolean iswrite = TRUE; boolean secondstage = FALSE; AArch64.Abort(toaddress, AlignmentFault(acctype, iswrite, secondstage)); if setsize != Align(setsize, TAG_GRANULE) then boolean iswrite = TRUE; boolean secondstage = FALSE; AArch64.Abort(toaddress, AlignmentFault(acctype, iswrite, secondstage)); integer tagstep; bits(4) tag; bits(64) tagaddr; if supports_option_a then while SInt(stagesetsize) < 0 do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(toaddress, setsize, 16); assert B <= -1*SInt(stagesetsize); assert B<3:0> == '0000'; Mem[toaddress + setsize, B, acctype] = Replicate(data, B); tagstep = B DIV 16; tag = AArch64.AllocationTagFromAddress(toaddress + setsize); while tagstep > 0 do tagaddr = toaddress + setsize + (tagstep-1) * 16; AArch64.MemTag[tagaddr, acctype] = tag; tagstep = tagstep - 1; setsize = setsize + B; stagesetsize = stagesetsize + B; if stage != MOPSStage_Prologue then X[n] = setsize; else while UInt(stagesetsize) > 0 do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(toaddress, setsize, 16); assert B <= UInt(stagesetsize); assert B<3:0> == '0000'; Mem[toaddress, B, acctype] = Replicate(data, B); tagstep = B DIV 16; tag = AArch64.AllocationTagFromAddress(toaddress); while tagstep > 0 do tagaddr = toaddress + (tagstep-1) * 16; AArch64.MemTag[tagaddr, acctype] = tag; tagstep = tagstep - 1; toaddress = toaddress + B; setsize = setsize - B; stagesetsize = stagesetsize - B; if stage != MOPSStage_Prologue then X[n] = setsize; X[d] = toaddress; if stage == MOPSStage_Prologue then X[n] = setsize; X[d] = toaddress;

Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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sz		0	1	1	1	0	1	1	1	0	Rs					x	x	1	0	0	1	Rn					Rd
																op2