SM3PARTW1 takes three 128-bit vectors from the three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information.
This instruction is implemented only when FEAT_SM3 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | Rm | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||
if !HaveSM3Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m]; bits(128) Vn = V[n]; bits(128) Vd = V[d]; bits(128) result; result<95:0> = (Vd EOR Vn)<95:0> EOR (ROL(Vm<127:96>,15):ROL(Vm<95:64>,15):ROL(Vm<63:32>,15)); for i = 0 to 3 if i == 3 then result<127:96> = (Vd EOR Vn)<127:96> EOR (ROL(result<31:0>,15)); result<(32*i)+31:(32*i)> = result<(32*i)+31:(32*i)> EOR ROL(result<(32*i)+31:(32*i)>,15) EOR ROL(result<(32*i)+31:(32*i)>,23); V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.