SM3TT1B takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:
The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9.
This instruction is implemented only when FEAT_SM3 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 1 | 0 | imm2 | 0 | 1 | Rn | Rd | |||||||||||||
if !HaveSM3Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer i = UInt(imm2);
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
| <imm2> |
Is a 32-bit element indexed out of <Vm>, encoded in "imm2". |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m]; bits(128) Vn = V[n]; bits(128) Vd = V[d]; bits(32) WjPrime; bits(128) result; bits(32) TT1; bits(32) SS2; WjPrime = Elem[Vm,i,32]; SS2 = Vn<127:96> EOR ROL(Vd<127:96>,12); TT1 = (Vd<127:96> AND Vd<63:32>) OR (Vd<127:96> AND Vd<95:64>) OR (Vd<63:32> AND Vd<95:64>); TT1 = (TT1 + Vd<31:0> + SS2 + WjPrime)<31:0>; result<31:0> = Vd<63:32>; result<63:32> = ROL(Vd<95:64>,9); result<95:64> = Vd<127:96>; result<127:96> = TT1; V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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