SM4 Encode takes input data as a 128-bit vector from the first source SIMD&FP register, and four iterations of the round key held as the elements of the 128-bit vector in the second source SIMD&FP register. It encrypts the data by four rounds, in accordance with the SM4 standard, returning the 128-bit result to the destination SIMD&FP register.
This instruction is implemented only when FEAT_SM4 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||
if !HaveSM4Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn);
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vn = V[n]; bits(32) intval; bits(128) roundresult; bits(32) roundkey; roundresult = V[d]; for index = 0 to 3 roundkey = Elem[Vn,index,32]; intval = roundresult<127:96> EOR roundresult<95:64> EOR roundresult<63:32> EOR roundkey; for i = 0 to 3 Elem[intval,i,8] = Sbox(Elem[intval,i,8]); intval = intval EOR ROL(intval,2) EOR ROL(intval,10) EOR ROL(intval,18) EOR ROL(intval,24); intval = intval EOR roundresult<31:0>; roundresult<31:0> = roundresult<63:32>; roundresult<63:32> = roundresult<95:64>; roundresult<95:64> = roundresult<127:96>; roundresult<127:96> = intval; V[d] = roundresult;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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