SM4 key updates
The SM4EKEY instruction reads four rounds of 32-bit input key values from each 128-bit segment of the first source vector, along with four rounds of 32-bit constants from the corresponding 128-bit segment of the second source vector. The four rounds of output key values are derived in accordance with the SM4 standard, and placed in the corresponding segments of the destination vector. This instruction is unpredicated.
ID_AA64ZFR0_EL1.SM4 indicates whether this instruction is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Zm | 1 | 1 | 1 | 1 | 0 | 0 | Zn | Zd | ||||||||||||
size<1> | size<0> |
if !HaveSVE() || !HaveSVE2SM4() then UNDEFINED; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckNonStreamingSVEEnabled(); integer segments = VL DIV 128; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for s = 0 to segments-1 bits(128) source = Elem[operand2, s, 128]; bits(32) intval; bits(8) sboxout; bits(32) const; bits(128) roundresult = Elem[operand1, s, 128]; for index = 0 to 3 const = Elem[source, index, 32]; intval = roundresult<127:96> EOR roundresult<95:64> EOR roundresult<63:32> EOR const; for i = 0 to 3 Elem[intval, i, 8] = Sbox(Elem[intval, i, 8]); intval = intval EOR ROL(intval, 13) EOR ROL(intval, 23); intval = intval EOR roundresult<31:0>; roundresult<31:0> = roundresult<63:32>; roundresult<63:32> = roundresult<95:64>; roundresult<95:64> = roundresult<127:96>; roundresult<127:96> = intval; Elem[result, s, 128] = roundresult; Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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