SMLSL, SMLSL2 (by element)

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

The SMLSL instruction extracts vector elements from the lower half of the first source register. The SMLSL2 instruction extracts vector elements from the upper half of the first source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001111sizeLMRm0110H0RnRd
Uo2

SMLSL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]

integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean unsigned = (U == '1'); boolean sub_op = (o2 == '1');

Assembler Symbols

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q 2
0 [absent]
1 [present]
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in size:

size <Ta>
00 RESERVED
01 4S
10 2D
11 RESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in size:Q:

size Q <Tb>
00 x RESERVED
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED
<Vm>

Is the name of the second SIMD&FP source register, encoded in size:M:Rm:

size <Vm>
00 RESERVED
01 0:Rm
10 M:Rm
11 RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Ts>

Is an element size specifier, encoded in size:

size <Ts>
00 RESERVED
01 H
10 S
11 RESERVED
<index>

Is the element index, encoded in size:L:H:M:

size <index>
00 RESERVED
01 H:L:M
10 H:L
11 RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(idxdsize) operand2 = V[m]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; element2 = Int(Elem[operand2, index, esize], unsigned); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); product = (element1 * element2)<2*esize-1:0>; if sub_op then Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; else Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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