Signed 8-bit integer matrix multiply-accumulate. This instruction multiplies the 2x8 matrix of signed 8-bit integer values in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element.
From Armv8.2 to Armv8.5, this is an optional instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rm | 1 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
| U | B | ||||||||||||||||||||||||||||||
if !HaveInt8MatMulExt() then UNDEFINED; case B:U of when '00' op1_unsigned = FALSE; op2_unsigned = FALSE; when '01' op1_unsigned = TRUE; op2_unsigned = TRUE; when '10' op1_unsigned = TRUE; op2_unsigned = FALSE; when '11' UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd);
| <Vd> |
Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(128) operand1 = V[n]; bits(128) operand2 = V[m]; bits(128) addend = V[d]; V[d] = MatMulAdd(addend, operand1, operand2, op1_unsigned, op2_unsigned);
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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