Signed integer sum of outer products and accumulate
The 8-bit integer variant works with a 32-bit element ZA tile.
The 16-bit integer variant works with a 64-bit element ZA tile.
The signed integer sum of outer products and accumulate instructions multiply the sub-matrix in the first source vector by the sub-matrix in the second source vector. In case of the 8-bit integer variant, the first source holds SVLS×4 sub-matrix of signed 8-bit integer values, and the second source holds 4×SVLS sub-matrix of signed 8-bit integer values. In case of the 16-bit integer variant, the first source holds SVLD×4 sub-matrix of signed 16-bit integer values, and the second source holds 4×SVLD sub-matrix of signed 16-bit integer values.
Each source vector is independently predicated by a corresponding predicate register. When an 8-bit source element in case of 8-bit integer variant or a 16-bit source element in case of 16-bit integer variant is Inactive, it is treated as having the value 0.
The resulting SVLS×SVLS widened 32-bit integer or SVLD×SVLD widened 64-bit integer sum of outer products is then destructively added to the 32-bit integer or 64-bit integer destination tile, respectively for 8-bit integer and 16-bit integer instruction variants. This is equivalent to performing a 4-way dot product and accumulate to each of the destination tile elements.
In case of the 8-bit integer variant, each 32-bit container of first source vector holds 4 consecutive column elements of each row of a SVLS×4 sub-matrix, and each 32-bit container of second source vector holds 4 consecutive row elements of each column of a 4×SVLS sub-matrix. In case of the 16-bit integer variant, each 64-bit container of first source vector holds 4 consecutive column elements of each row of a SVLD×4 sub-matrix, and each 64-bit container of second source vector holds 4 consecutive row elements of each column of a 4×SVLD sub-matrix.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
It has encodings from 2 classes: 32-bit and 64-bit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda | |||||||||||||
u0 | u1 | S |
if !HaveSME() then UNDEFINED; integer esize = 32; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(ZAda); boolean sub_op = FALSE; boolean op1_unsigned = FALSE; boolean op2_unsigned = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | ZAda | ||||||||||||||
u0 | u1 | S |
if !HaveSMEI16I64() then UNDEFINED; integer esize = 64; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(ZAda); boolean sub_op = FALSE; boolean op1_unsigned = FALSE; boolean op2_unsigned = FALSE;
<ZAda> |
For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field. |
For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field. |
<Pn> |
Is the name of the first source scalable predicate register P0-P7, encoded in the "Pn" field. |
<Pm> |
Is the name of the second source scalable predicate register P0-P7, encoded in the "Pm" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckStreamingSVEAndZAEnabled(); integer dim = VL DIV esize; bits(PL) mask1 = P[a]; bits(PL) mask2 = P[b]; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(dim*dim*esize) operand3 = ZAtile[da, esize]; bits(dim*dim*esize) result; integer prod; for row = 0 to dim-1 for col = 0 to dim-1 bits(esize) sum = Elem[operand3, row*dim+col, esize]; for k = 0 to 3 if ElemP[mask1, 4*row + k, esize DIV 4] == '1' && ElemP[mask2, 4*col + k, esize DIV 4] == '1' then prod = (Int(Elem[operand1, 4*row + k, esize DIV 4], op1_unsigned) * Int(Elem[operand2, 4*col + k, esize DIV 4], op2_unsigned)); if sub_op then prod = -prod; sum = sum + prod; Elem[result, row*dim+col, esize] = sum; ZAtile[da, esize] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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