Signed saturating decrement scalar by count of true predicate elements
Counts the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the source general-purpose register's signed integer range. A 32-bit saturated result is then sign-extended to 64 bits.
It has encodings from 2 classes: 32-bit and 64-bit
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | Pm | Rdn | ||||||||
| D | U | sf | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = FALSE; integer ssize = 32;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | Pm | Rdn | ||||||||
| D | U | sf | |||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = FALSE; integer ssize = 64;
| <Xdn> |
Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. |
| <Pm> |
Is the name of the source scalable predicate register, encoded in the "Pm" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Wdn> |
Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(ssize) operand1 = X[dn]; bits(PL) operand2 = P[m]; bits(ssize) result; integer count = 0; for e = 0 to elements-1 if ElemP[operand2, e, esize] == '1' then count = count + 1; integer element = Int(operand1, unsigned); (result, -) = SatQ(element - count, ssize, unsigned); X[dn] = Extend(result, 64, unsigned);
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.