Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
The results are truncated. For rounded results, see SQRDMULH.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | size | L | M | Rm | 1 | 1 | 0 | 0 | H | 0 | Rn | Rd | ||||||||||||
op |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean round = (op == '1');
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0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 1 | 1 | 0 | 0 | H | 0 | Rn | Rd | ||||||||||||
op |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean round = (op == '1');
<V> |
Is a width specifier,
encoded in
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
|
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register,
encoded in
|
<Ts> |
Is an element size specifier,
encoded in
|
<index> |
Is the element index,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; element2 = SInt(Elem[operand2, index, esize]); for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); product = (2 * element1 * element2) + round_const; // The following only saturates if element1 and element2 equal -(2^(esize-1)) (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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