SQDMULH (vectors)

Signed saturating doubling multiply high (unpredicated)

Multiply then double the corresponding signed elements of the first and second source vectors, and place the most significant half of the results in the corresponding elements of the destination vector register. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm011100ZnZd
R

SQDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSVE2() && !HaveSME() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 integer element1 = SInt(Elem[operand1, e, esize]); integer element2 = SInt(Elem[operand2, e, esize]); integer res = 2 * element1 * element2; Elem[result, e, esize] = SignedSat(res >> esize, esize); Z[d] = result;


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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