Signed saturating increment scalar by multiple of 8-bit predicate constraint element count
Determines the number of active 8-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the scalar destination. The result is saturated to the source general-purpose register's signed integer range. A 32-bit saturated result is then sign-extended to 64 bits.
The named predicate constraint limits the number of active elements in a single predicate to:
* A fixed number (VL1 to VL256)
* The largest power of two (POW2)
* The largest multiple of three or four (MUL3 or MUL4)
* All available, implicitly a multiple of two (ALL).
Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
It has encodings from 2 classes: 32-bit and 64-bit
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | imm4 | 1 | 1 | 1 | 1 | 0 | 0 | pattern | Rdn | |||||||||||
size<1> | size<0> | sf | D | U |
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1; boolean unsigned = FALSE; integer ssize = 32;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | imm4 | 1 | 1 | 1 | 1 | 0 | 0 | pattern | Rdn | |||||||||||
size<1> | size<0> | sf | D | U |
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1; boolean unsigned = FALSE; integer ssize = 64;
<Xdn> |
Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. |
<Wdn> |
Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. |
<imm> |
Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field. |
CheckSVEEnabled(); integer count = DecodePredCount(pat, esize); bits(ssize) operand1 = X[dn]; bits(ssize) result; integer element1 = Int(operand1, unsigned); (result, -) = SatQ(element1 + (count * imm), ssize, unsigned); X[dn] = Extend(result, 64, unsigned);
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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